1. Field of the Invention
The present disclosure relates generally to the design and manufacture of Integrated Circuits (ICs). More specifically, the present invention relates to the design of Random Access Memory (RAM) ICs.
2. Description of the Related Art
Semiconductor memory is typically laid out as an array of core cells, such that each individual core cell is coupled to a wordline and a pair of differential bitlines, as well as a power and ground connection. To read or write data from or to a selected core cell requires addressing circuitry for selecting the core cell, wordline drivers for driving the selected wordline and sense amplifiers for amplifying the signals that are read from the selected core cell and output buffers.
FIG. 1a is a simplified diagram of a memory 10 consisting of an array of core cells 12. Each of the core cells 12 is connected to a pair of bitlines, such as bitline (BL) 14 and a complementary bitline (/BL) 16. Each core cell is also electrically coupled to other core cells 12 along horizontal wordlines (WL) 18. Sense amplifying circuitry is usually implemented to read data, and write drivers to write data into selected core cells 12.
Although conventional sense amplifying circuitry has worked well in the past for sensing voltage differentials between the bitlines 14 and 16, higher performance memory now requires the ability to sense very small voltage differentials between the bitlines. Previously, sense amplifiers were required to sense voltage differentials of approximately 500 millivolts (mV) between the bitlines 14 and 16 to read data that was stored in a particular core cell 12. Due to expected fabrication imperfections and circuit layout constraints, there is usually a voltage offset between the bitlines 14 and 16. Voltage offsets are typically between 5 to 30 millivolts.
Although such offsets are typical, they were insignificant compared to the 500 millivolt voltage differential required for triggering amplification by a sense amplifier. However, higher performance memory now requires that amplification by the sense amplifier occur at much faster rates. Current sense amplifiers must respond more quickly and are required to sense voltage differentials of between about 15 and 60 millivolts across the bitlines. Unfortunately, typical voltage offsets in the range of 5 to 30 millivolts will necessarily begin to hamper the speed at which sense amplification may occur.
FIG. 1b shows a pair of exemplary bitlines 14 and 16 that are interconnecting successive core cells 12 in the vertical column direction. Also shown are representative wordlines 18 that horizontally interconnect each of the core cells 12. The core cells 12 are typically symmetric data latching circuits that have cross-coupled inverters and passgate transistors that are coupled to respective wordlines 18. Although the core cells 12 are symmetric in their schematic circuit representation, the resulting geometric shape and layout orientation on a semiconductor substrate will usually be less than perfectly symmetric.
As a result, the capacitive loading experienced on each of the respective bitlines 14 and 16 will not be equal. When the voltage at point 32 is driven to rail voltage (Vdd), capacitive coupling of C1 will occur between pre-charged transistors 30 and the bitlines 14 and 16. As pictorially shown in FIG. 1b, if the capacitive loading in the bitline 14 is “C+ΔC” and the capacitive loading in the complementary bitline 16 is “C,” then there will be a voltage offset of ΔV between bitlines 14 and 16 due to miller coupling capacitance. Other contributions to the offset are the result of process variation in the fabrication of the memory and different device size and strength. Bitline 14 may have a voltage of V and the complementary bitline 16 may have a voltage of V+ΔV. It is this voltage offset that becomes problematic when voltage sensing between the bitlines is required at lower voltage differentials. This problem occurs while reading a low on complementary bitline 16, when the complementary bitline has a voltage of V+ΔV.
FIG. 1c shows bitline 14 and the complementary bitline 16 graphed in terms of voltage and time, and illustrating that sense application will occur when accessing data of a particular core cell 12. In this example, the voltage offset is shown to be 15 millivolts (mV) between the bitline 14 and the complementary bitline 16. When sensing the digital data that is stored in this particular core cell, the complementary bitline 16 will begin to fall at time T0. The complementary bitline 16 must first cross the bitline 14 at time T1. Therefore, a higher performance sense amplifier that is required to detect about 30 mV difference between the bitlines, and which must also cope with voltage offsets of 15 mV, will not commence its amplification until time T3.
If there were no voltage offset between the bitlines as represented by a complimentary bitline 16′, a sense amplifier would be able to sense a voltage differential of 30 mV much more rapidly at a time T2. Thus, even very small voltage offsets have substantial performance deteriorating ramifications. Unfortunately, conventional memory device performance is limited by the expected fabrication imperfections and layout constraints that produce imbalances in capacitive loading of the bitlines of each core cell 12.
The design and fabrication of both static RAM (SRAM) with single and multiple ports and dynamic RAM (DRAM) is well known. A schematic of a known SRAM single port core cell is illustrated in FIG. 2. Core cell 20 is comprised of two inverters 21 the output of each inverter being coupled to the input of the other inverter. Inverters 21 store the binary “0” or “1” that forms the content of the core cell. Each core cell 20 is coupled to a pair of bit lines 23, which bit lines carry the data into and out of the core cell, and a word line 25, which word line indicates when it is asserted that either a new value will be written to core cell 20 or the contents of core cell 20 will be read. Access transistors 27 switch on to permit data placed on bit lines 23 to flow into inverters 21 of core cell 20 or out of core cell 20 onto the bit lines when core cell 20's word line 25 is asserted. This type of core cell is sometimes called a 6T cell, as it is fabricated from six transistors (each inverter 21 requires two transistors and the two access transistors 27). The design and fabrication of core cell 20 and similar core cells are known to those of skill in the art.
Dual port SRAM core cells are also known. FIG. 3 is a schematic of a dual port core cell 50 that is very similar to the single port core cell illustrated in FIG. 2. In all figures referenced by this specification, similar parts have the same part number. The main differences between a single port and a dual port core cell are the provision of a second word line 29 and a second set of bit lines 31. The addition of second word line 29 requires an additional two access transistors 27 coupled to second word line 29, the bit lines 23 and 31 and the inverters. As with single port SRAM core cells, dual port core cells are known and their design and fabrication require no extensive description here.
A commonly used IC layout used to fabricate the dual port core cell shown in FIG. 3 is illustrated in FIG. 4. Approximately ⅔rds of the cell's area comprises an p-type substrate 43 for the fabrication of n-type transistors and the other ⅓rd  of the cell's surface area comprises a n-type substrate 45 for the fabrication of p-type transistors. These n-type and p-type transistors are then coupled together to form inverters 21. Trace 41 in FIG. 4 indicates the areas of the cell that are interconnected to form one of the inverters. Metal interconnections are run through and across the cell to various points, creating the bit lines, the word lines and the power and ground lines. The metal interconnections are not illustrated in FIG. 4.
Although well known, dual port memory core cells laid out in the manner shown in FIG. 4 have certain performance limitations and problems. The height (indicated as “H” in FIG. 4) of these dual port memory core cells is great enough so that cumulatively the bit lines running to the transistors in a column of core cell have sufficient capacitance to affect the speed of the core cell materially. The bitlines are also typically closer together than is optimal, resulting in charge coupling between the bitlines, which reduces the speed of the core cell. Given the layout of known SRAM core cells, it is not possible to move the bitlines sufficiently far apart to eliminate this problem. Capacitance matching on the various bitlines is also difficult and limited space in the core cell prevents moving bitlines around to reduce this problem.
A core cell for either a dual port or single port SRAM memory with reduced height bit lines and reduced charge coupling on the bitlines would be a desirable improvement.